Bluetooth access code assisted initial DC estimation and frame synchronization

ABSTRACT

A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This patent application is a continuation of U.S. patent applicationSer. No. 10/027,558, filed on Oct. 22, 2001 now U.S. Pat. No. 7,035,350.The above-identified application is hereby incorporated by reference inits entirety.

RELATED APPLICATIONS

The present application is related to commonly owned and assigned,patent application Ser. No. 10/035,567, entitled System and Method forDC Offset Compensation and Bit Synchronization, which is filed on evendate herewith and is incorporated herein by reference in its entirety.In this patent application, we describe a method that can be used toprovide an accurate initial DC offset for the automatic DC tracker, thusimproving the DC tracker's initial converge time and estimate stability.In the mean time, since the initial DC estimation is based on some knownframe synchronization (sync) pattern, the method also performs andachieves frame detection. This patent application can therefore beapplied to all wireless communication systems that use packet data withsync pattern in front.

FIELD OF THE INVENTION

The present invention relates to wireless communication devices andprotocols. In particular, but not by way of limitation, the presentinvention relates to systems and methods for improving the quality andcommercial appeal of wireless communications.

BACKGROUND OF THE INVENTION

Wireless communications and wireless communication devices are at thecenter of many important technological advancements. As theproliferation of these wireless devices increases, the efficiency andaccuracy of the communications therebetween becomes vital to thecommercial success of particular devices and particular communicationsprotocols. One protocol that is showing great promise is Bluetooth(described in, for example, The Specification of the Bluetooth System,v1.0 B, Dec. 1, 1999), which is a wireless protocol that describes howmobile phones, computers, PDAs, peripherals and other devices caninterconnect using a short-range wireless connection. The Specificationof the Bluetooth System, v1.0 B, Dec. 1, 1999, which is publiclyavailable, is incorporated herein by reference.

To implement Bluetooth and other such wireless protocols, a devicereceiving a transmitted signal is required to recover transmitted bitpatterns. The basic recovering process involves waveform demodulation,DC compensation, bit synchronization and bit detection. Waveformdemodulation usually is implemented in a radio module and is wirelessprotocol dependent. DC compensation can be implemented either in theradio module or in the baseband. It is a critical process, however, forachieving correct bit synchronization and detection. Bit synchronizationand detection are usually implemented in the baseband and are common tomany different wireless receivers. An automatic DC tracker and a bitsynchronizer have been described in commonly owned and assigned patentapplication Ser. No. 10/035,567, filed Oct. 22, 2001.

DC offset is a variation in the intended DC voltage of the baselinesignal caused, for example, by frequency drift in received BluetoothGFSK signals. Present devices compensate for these imperfections inincoming signals using a variety of means—none of which are completelysatisfactory. For example, certain electronic devices use analogcomponents to calculate the DC offset, while other devices use digitalcomponents. The analog DC trackers usually are implemented as lowpass RCfilters, while conventional digital approaches require a select numberof bits to be buffered before any DC offset can be calculated.

The DC tracking accuracy of both conventional analog and digitalcircuits is affected by the incoming bit patterns. For instance, when astring of high values, e.g., “1s,” is received the computed DC offsetwill be adjusted to a higher value even though the actual DC offset hasnot changed. This adjustment occurs because most automatic DC trackersassume an even distribution of high and low values in the receivedsignal. In addition, the DC tracking accuracy and associated estimatevariance are sensitive to selected time constant in analog filters. Forconventional digital DC tracker, they are functions of the selectedbuffer size.

Although present analog and digital approaches to computing DC offsetsfor wireless communications are functional, they are not sufficientlyaccurate or otherwise satisfactory. Accordingly, a system and method areneeded to address the shortfalls of present technology and to provideother new and innovative features.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention that are shown in thedrawings are summarized below. These and other embodiments are morefully described in the Detailed Description section. It is to beunderstood, however, that there is no intention to limit the inventionto the forms described in this Summary of the Invention or in theDetailed Description. One skilled in the art can recognize that thereare numerous modifications, equivalents and alternative constructionsthat fall within the spirit and scope of the invention as expressed inthe claims.

The present invention can provide a system and method for calculating DCoffset. In one embodiment, the present invention includes an electronicdevice with an integrated receiver module. The receiver module can takeadvantage of a known frame sync pattern, such as the Bluetooth accesscode, to approximate an initial DC offset. Although this receiver modulecan be implemented in a variety of ways, one implementation includes aradio module, an analog-to-digital (A/D) converter, an initial DCestimator, a DC tracker, and a bit synchronizer. Other implementationsmay remove the initial DC estimator and use the DC tracker only, orremove the DC tracker and freeze the initial DC estimator output for theentire data frame. In either case, less hardware is required.

In an exemplary mode of operation, an electronic device, such as acellular phone, initially receives an RF signal that can be demodulatedand down-converted a baseband signal in the radio module. The A/Dconverter is then used to sample and convert the baseband signal fromanalog to digital form. As mentioned previously, the first portion ofthe received usually includes a sync pattern. Samples corresponding tothe sync pattern or a part of the sync pattern are used to calculate aDC summation (DC_(sum)). Using only a part of the sync pattern toperform this calculation can reduce the amount of hardware andprocessing time required.

The DC_(sum) can be divided by the number of samples actually used inthe summation to determine an average (DC_(avg)) value. Because thenumber of high bits and low bits may not be equal in the part of thesync pattern used for the calculation, a straight average does notnecessarily provide an accurate estimation of the DC offset. Tocalculate a more accurate estimate, the DC_(avg) can be adjusted by acompensation factor (comp_fac) generated from the chosen portion of theknown sync pattern.

Using the calculated compensation factor, the compensated DC average(DC_(avg) _(—) _(comp)) can be represented byDC _(avg) _(—) _(comp)(k)≈DC _(avg)(k)+comp_facwhere k is the current sample time index.

Moreover, using the DC_(avg) _(—) _(comp)(k), a bit slicer can beapplied to determine the binary value (0 or 1) of the received syncpattern samples contained in DC_(sum). That is, if the sample value isgreater than DC_(avg) _(—) _(comp)(k), it corresponds to a binary 0,otherwise it is a binary 1. A correlator module can correlate the bitslicer output with the chosen portion of the known sync pattern todetermine whether a potential frame detection has occurred. For example,when a threshold number of the received sync pattern bits—adjustedaccording to the DC_(avg) _(—) _(comp)—match corresponding bits in theknown sync pattern, a potential frame detection can be declared.

To confirm the potential frame detection, the DC_(avg) _(—) _(comp)(k)is frozen at the time sample when the potential frame detection wasdeclared. Next, a symbol peak is identified using the next set of (N−1)digital samples of the received signal. Here, N is the number ofover-sampling compared to the nominal symbol rate. Using the frozenDC_(avg) _(—) _(comp)(k) and the identified symbol peak, a secondportion of the received sync pattern is correlated with the rest of theknown sync pattern. If a threshold number of bits in the second portionof the received pilot signal and the known sync pattern and the knownsync pattern match, a formal frame detection is declared and theDC_(avg) _(—) _(comp)(k) is generated as an output for the followingprocess, either as an initial estimate for a DC tracker or used as afrozen DC value for the rest of the data packet. Otherwise, the entireprocess is restarted and a new DC_(avg) _(—) _(comp)(k) is calculatedusing a next sample time.

As previously stated, the above-described embodiments andimplementations are for illustration purposes only. Numerous otherembodiments, implementations, and details of the invention are easilyrecognized by those of skill in the art from the following descriptionsand claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Various objects and advantages and a more complete understanding of thepresent invention are apparent and more readily appreciated by referenceto the following Detailed Description and to the appended claims whentaken in conjunction with the accompanying Drawings wherein:

FIG. 1 illustrates various electronic devices with integrated receivermodules constructed in accordance with the principles of the presentinvention;

FIG. 2 illustrates an implementation of the receiver module of thepresent invention in greater detail;

FIG. 3 illustrates an alternative implementation of the receiver moduleshown in FIG. 2;

FIG. 4 illustrates a more detailed exemplary implementation (based onBluetooth's sync pattern) of the initial DC offset estimation moduleshown in FIG. 3;

FIGS. 5 and 6 are exemplary circuit diagrams of an implementation of theinitial DC estimation module shown in FIGS. 2 and 4;

FIG. 7 illustrates an exemplary implementation of the frame detectormodule shown in FIG. 4; and

FIG. 8 is a flow chart of one method of operating an embodiment of thepresent invention based on Bluetooth sync pattern.

DETAILED DESCRIPTION

Referring now to the drawings, where like or similar elements aredesignated with identical reference numerals throughout the severalviews, and referring in particular to FIG. 1, it illustrates examples ofelectronic devices with integrated receiver modules 105 constructed inaccordance with the principles of the present invention. Although only acomputer 110, a PDA (personal digital assistant) 115, cell phone 120 andperipheral device 125 are illustrated, the present invention can includeany type of wireless-enabled device and should not be limited to thosedevices shown. The receiver modules 105 in these various devices caninclude, for example, ASICs (application specific integrated circuits),software instructions, general purpose processors, or any combinationthereof.

FIG. 2 illustrates an implementation of the receiver module of thepresent invention in greater detail. In this implementation, a RF signal(or any other type of signal) is received at the radio module 130, whichdemodulates and downconverts the RF signal to a baseband signal. Theradio module 130 then passes the baseband signal to the A/D converter135, where the analog signal is converted to a digital signal. The A/Dconverter 135 then passes the digital signal to the initial DCestimation module 140, which determines the DC offset within the chosenportion of the received sync pattern. This DC offset can be passed as aninitial DC estimate to a DC tracker 145 that monitors long term DC driftand generates a corresponding DC offset values continuously. Data fromthe DC tracker 145 can be provided to the bit synchronizer 147.

Referring now to FIG. 3, it illustrates a more detailed implementationof the initial DC estimation module 140 shown in FIG. 2. In thisembodiment, the initial DC estimation module 140 includes twocomponents: a DC offset module 150 and a frame detector module 155. TheDC offset module 150 is configured to determine a DC offset based uponat least a portion of a known sync pattern. In one embodiment, the DCestimation module 150 is configured to determine the DC offset using thefirst 34 bits of the 64 bit Bluetooth synchronization word and to detecta potential frame. The reason for using the first 34 bits of thesynchronization word is that the bit pattern in the first 34 bits ismore evenly distributed between “1”s and “0”s than in the latter 30bits.

The frame detector module 155 is configured to confirm a potential framedetection by the DC offset module 150. In the preferred embodiment, theframe detector module 155 confirms the frame detection based upon thelast 30 bits of the Bluetooth synchronization word.

FIG. 4 illustrates a more detailed implementation of the DC offsetmodule 150 shown in FIG. 3. This embodiment of the DC offset module 150includes 34 storage locations (labeled as symbol storage 0 throughsymbol storage 33) for storing sample values related to bits 0 through33 of the received synchronization word. For example, symbol storage 0could include N individual storage locations to store the DC value ofthe received signal sampled at N times the symbol rate. Each of thesymbol storage locations is associated with a comparator (labeled ascomparator 0 through comparator 33.) Each of the sample values for aparticular symbol are passed from a symbol storage to the appropriatecomparator. The output of each individual comparator is determined by

${z_{34}\left( {k,j} \right)} = \left\{ \begin{matrix}{1,} & {{{y\left( {k + {\left( {j - 34} \right) \cdot 5}} \right)} < {{DC}_{avg\_ comp}(k)}},} & {{j = 1},2,\ldots\mspace{11mu},34} \\{0,} & {{y\left( {k + {\left( {j - 34} \right) \cdot 5}} \right)} > {{DC}_{avg\_ comp}(k)}} & \;\end{matrix} \right.$where k is the current sample time index, y(i) is the output of the A/Dconverter 135, and DC_(avg) _(—) _(comp)(k) is the compensated DCaverage, which is described in detail below.

The DC_(avg) _(—) _(comp) calculator 170 calculates the DC_(avg) _(—)_(comp) value used by the comparators. If the sampling rate results in Nsamples per symbol, the DC_(avg) _(—) _(comp) calculator 170 would use34×N running samples from the A/D converter 135. However, to reducehardware complexity—by allowing bit shifting to replace complexmultiplication—32×N samples from the A/D converter 135 can be used tocalculate the DC average (DC_(avg)) which can be approximated by

${{DC}_{sum}(k)} = {\sum\limits_{i = {k - {32 \times n} + 1}}^{k}\;{y(i)}}$$\begin{matrix}{{{DC}_{avg}(k)} = {{{DC}_{sum}(k)}/\left( {N \times 32} \right)}} \\{= {\left( {{{DC}_{sum}(k)}/N} \right) ⪢ 5}}\end{matrix}$where k is the current sample time index and y(i) is the output from theA/D converter 135. If N=4, then

${{DC}_{sum}(k)} = {\sum\limits_{i = {k - {32 \times 4} + 1}}^{k}\;{y(i)}}$$\begin{matrix}{{{DC}_{avg}(k)} = {{{DC}_{sum}(k)}/\left( {4 \times 32} \right)}} \\{= {\left( {{{DC}_{sum}(k)}/4} \right) ⪢ 5}} \\{= {{{DC}_{sum}(k)} ⪢ 7.}}\end{matrix}$

Because the bits of the received synchronization word may have anon-ideal bit pattern that introduces DC bias, the DC_(avg) should becorrected by a compensation factor (comp_fac.) This compensation factorcan be calculated using the corresponding 32 bits of the synchronizationword ascomp_fac=A _(peak)(number of 1's−number of 0's) /32.where A_(peak) is the sample peak amplitude of the output from the A/Dconverter 135. Assuming bit inversion, the compensated DC averagebecomesDC _(avg) _(—) _(comp)(k)≈DC _(avg)(k)+comp_fac.

Still referring to FIG. 4, the output from the individual comparatorscan be latched in storage devices, DC corrected symbol 0 through DCcorrected symbol 33 (but do not necessarily need to be) and passed to acorrelation module 160, which compares the output of the individualcomparators with the known synchronization word to identify a potentialframe detection. A potential frame detection can be declared at anysample time assuming a threshold number of bits of the DC correctedsamples—as stored in DC corrected symbol 0 through DC corrected symbol33—match the corresponding bits in the known synchronization word.

After a potential frame has been detected, the value for the DC_(avg)_(—) _(comp)(k) is frozen and the next symbol peak is identified by thepeak identifier 165. For example, the correlation process could becontinued for the next (N−1) samples to identify matching of the first34 bits of the synchronization word. Assuming that the first 34 bitcorrelation match occurred at sample time n and N=4, the following rulescan be used to determine the symbol peak location based on thecorrelation pattern over the four sample period (n to n+3):

-   -   1. If correlation matches occurred at both time n and n+3,        regardless of what happened in between, the symbol peak is at        n+2;    -   2. If the only matches occur at time n, the symbol peak is at n;    -   3. If a correlation match occurred at time n+3, and either time        n+1 or n+2 or both also had correlation matches, the symbol peak        is at n+2; and    -   4. For all other cases, the symbol peak is at n+1.

FIGS. 5 and 6 illustrate an implementation of the DC offset module shownin FIGS. 2 and 4. In this implementation, symbol storage 0 isrepresented by latches 00 through 03; symbol storage 1 is represented bylatches 10 through 13; . . . symbol storage 32 is represented by latches320 through 323; and symbol storage 33 is represented by latches 330through 333. Similarly, comparator 0, comparator 1, . . . comparator 32,and comparator 33 are represented by the corresponding groupings of fourcomparators 175. Although only four latches and only four comparatorsare shown per symbol storage, the number of latches and comparators canbe easily varied according to the sample rate.

The output from each latch is passed to the corresponding comparator 175and compared against DC_(avg) _(—) _(comp), which is an input to eachcomparator 175. The output from each comparator 175 is then passed toone of the correlation modules shown in FIG. 6. For example, the outputsb00, b10, . . . , b330 are passed to correlator 0; the outputs b01, b11,. . . , b331 are passed to correlator 1; and so on. In other words, thefirst sample from each symbol storage is passed to a first correlationmodule, the second sample to a second correlation module, the thirdsample to a third correlation module, and the fourth sample to a fourthcorrelation module.

At each of the four correlation modules, the DC corrected samples arecompared against the known synchronization word. When a threshold numberof bits are matched, the appropriate line is signaled, the DC_(avg) _(—)_(comp)(k) value is frozen, and a potential frame detection is declared.

Referring now to FIG. 7, it illustrates a block diagram of the framedetection module 155 of FIG. 4. Once the DC offset module 150 declares apotential frame detection, the frame detector module 155 uses the frozenDC_(avg) _(—) _(comp)(n) (n being the time at which a potential framedetection is declared) and identified symbol peak to verify the framedetection. In this embodiment, for example, samples corresponding tobits 34-63 of the received synchronization word are stored incorresponding symbol storage locations, symbol storage 34 through symbolstorage 63. These samples are passed to the appropriate comparators,comparator 34 through comparator 63, where the output can be expressedas

${z_{30}\left( {k,j} \right)} = \left\{ \begin{matrix}{1,} & {{{y\left( {n^{\prime} + {j \cdot N}} \right)} < {{DC}_{avg\_ comp}(n)}},} & {{j = 1},2,\ldots\mspace{11mu},30} \\{0,} & {{y\left( {n^{\prime} + {j \cdot N}} \right)} > {{DC}_{avg\_ comp}(n)}} & \;\end{matrix} \right.$where n′ is the current symbol peak location and n is the sample time atwhich the DC offset module 150 declared the first 34 bit correlationmatch.

The output from the individual comparators is then passed to thecorrelation module 185 where each comparator's output can be comparedagainst the corresponding bit of the last 30 bits of the knownsynchronization word. If the number of matched bits between the outputfrom the comparators and the last 30 bits of the known synchronizationword are greater than or equal to a threshold value, a frame detectionis declared and DC_(avg) _(—) _(comp)(n) can be passed to a long-term DCtracker 145 as an initial DC offset estimate. Alternatively, if thethreshold value is not crossed, the DC_(avg) _(—) _(comp)(k) value isunfrozen and the calculation of the DC offset estimation based on thefirst 34 bits of the synchronization word is restarted.

FIG. 8 is a flowchart of one method of operating the present invention.This method is described in terms of the Bluetooth protocol. However,one skilled in the art can easily recognize that this method could beadapted to operate for virtually any wireless protocol—especially thoseusing a pilot signal or a synchronization word.

Initially, an electronic device computes a compensation factor using thefirst 32 bits of known synchronization word (step 190). Thiscompensation factor can be expressed ascomp_fac=A _(peak)(number of 1's−number of 0's)/32.At some point, that electronic device receives an RF signal includingthe synchronization word (step 195). This RF signal is then demodulatedand downconverted to a baseband signal which is in turn converted fromanalog to digital form (steps 200 and 205). Samples of the first 34 bitsof the synchronization word are then taken and stored (step 190).

Next, the DC_(sum) is calculated using 32×N samples. Although the first34×N (N being the number of oversampling as compared to the nominalsymbol rate) running samples from the A/D converter can be stored,hardware complexity can be reduced by using only 32×N samples in thecalculations. The DC_(sum) can be estimated by

${{DC}_{sum}(k)} = {\sum\limits_{i = {k - {32 \times N} + 1}}^{k}\;{y(i)}}$where k is the sample time index and y(i) is the output from the A/Dconverter 135. Using this DC_(sum), a DC_(avg) can be estimated (step215). DC_(avg) can be represented asDC _(avg)(k)=DC _(sum)(k)/(N×32).Finally, the compensated DC average can be calculated (step 220) byDC _(avg) _(—) _(comp)(k)≈DC _(avg)(k)+comp_fac

Next, the received data, as DC adjusted and bit sliced, can be comparedagainst the known synchronization word to determine if there is acorrelation (step 225). When the number of matched bits between the bitsliced data and the known synchronization word is greater than or equalto a threshold (step 230), a potential frame detection can be declaredand branch 235 is followed. Otherwise, branch 240 is followed and theDC_(sum)(k) is recomputed for the next sample time.

Assuming that the threshold value has been crossed and branch 235followed, the DC_(avg) _(—) _(comp)(k) for the current sample time isfrozen (step 245) and a symbol peak is located (step 250). Assuming thatthe potential frame detection was declared at sample time n and N=4, thefollowing rules determine the symbol peak location based on a continuedcorrelation over the next five sample period (n to n+4):

-   -   1) If correlation matches occurred at both time n and n+4,        regardless of what happened in between, the symbol peak is at        n+2;    -   2) If the only matches occur at time n, the symbol peak is at n;    -   3) For all other cases, if the symbol peak is at n+1 or n+2 or        both also had correlation matches, the symbol peak is at n+2;        and    -   4) For all other cases, the symbol peak is at n+1.

Next, the potential frame detection is verified by storing samples ofthe last 30 bits of the 64 bit synchronization word (step 255). These 30bits are then correlated with the remaining 30 bits of the knownsynchronization word (step 260 and 265). If the number of matched bitsis greater than or equal to a threshold value, a frame detection isdeclared (step 280) and a DC_(avg) _(—) _(comp)(n) is passed to along-term DC tracker (step 285). Otherwise, branch 275 is followed andthe DC_(avg) _(—) _(comp)(k) is unfrozen and the process repeated.

In conclusion, the present invention provides, among other things, asystem and method for optimizing wireless communication systems anddevices. Although the present system is described primarily withrelation to Bluetooth, the present invention can be adapted to work withvirtually any type of wireless protocol. Those skilled in the art canreadily recognize that numerous variations and substitutions may be madein the invention, its use and its configuration to achieve substantiallythe same results as achieved by the embodiments described herein.Accordingly, there is no intention to limit the invention to thedisclosed exemplary forms. Many variations, modifications andalternative constructions fall within the scope and spirit of thedisclosed invention as expressed in the claims.

1. A method for operating a wireless Bluetooth-enabled communicationdevice, comprising: computing a compensated DC average for a firstplurality of bits of an incoming pilot signal using a DC compensationfactor and a DC average; adjusting an indication of a received firstplurality of bits according to the computed compensated DC average;comparing the adjusted indication of the received first plurality ofbits with corresponding bits of a known pilot signal; and responsive toa threshold number of bits of the adjusted indication of the receivedfirst plurality of bits matching the corresponding bits of the knownpilot signal, outputting the compensated DC average for the firstplurality of bits.
 2. The method according to claim 1, comprising:locating a symbol peak in a received second plurality of bits of theincoming pilot signal; and using the symbol peak to determine a symboltiming of the incoming pilot signal.
 3. The method according to claim 2,comprising: adjusting an indication of a received third plurality ofbits according to the computed compensated DC average; comparing theadjusted indication of the received third plurality of bits withcorresponding bits of the known pilot signal; and responsive to thethreshold number of bits of the adjusted indication of the receivedfirst plurality of bits matching the corresponding bits of the knownpilot signal and responsive to a threshold number of bits of theadjusted indication of the received third plurality of bits matching thecorresponding bits of the known pilot signal, providing the compensatedDC average for the first plurality of bits to a DC tracker.
 4. Themethod according to claim 1, comprising: outputting the compensated DCaverage for the first plurality of bits to a DC tracker.
 5. The methodaccording to claim 1, wherein the known pilot signal comprises a framesync pattern.
 6. A wireless communication device, comprising: a receiverthat is configured to compute a compensated DC average for a firstplurality of bits of an incoming pilot signal using a DC compensationfactor and a DC average, configured to adjust an indication of areceived first plurality of bits according to the computed compensatedDC average, configured to compare the adjusted indication of thereceived first plurality of bits with corresponding bits of a knownpilot signal, and configured to provide the compensated DC average forthe first plurality of bits in response to a threshold number of bits ofthe adjusted indication of the received first plurality of bits matchingthe corresponding bits of the known pilot signal.
 7. The wirelesscommunication device according to claim 6, wherein the receiver isconfigured to locate a symbol peak in a received second plurality ofbits of the incoming pilot signal; and wherein the receiver isconfigured to use the symbol peak to determine a symbol timing of theincoming pilot signal.
 8. The wireless communication device according toclaim 6, wherein the receiver comprises a Bluetooth-enabled receiver. 9.A method for operating a wireless Bluetooth-enabled communicationdevice, comprising: computing a compensated DC average using a DCaverage and a DC compensation factor; determining whether a thresholdnumber of bits of a first portion of a received synchronization word asadjusted by the DC compensation factor match corresponding bits in aknown synchronization word; and responsive to a threshold number of bitsof the first portion of the received synchronization word as adjusted bythe DC compensation factor matching the corresponding bits in the knownsynchronization word, providing the compensated DC average to an offsettracking device.
 10. The method according to claim 9, comprising:determining whether a threshold number of bits of a second portion ofthe received synchronization word as adjusted by the DC compensationfactor match corresponding bits in the known synchronization word; andresponsive to a threshold number of bits of the second portion of thereceived synchronization word as adjusted by the DC compensation factormatching the corresponding bits in the known synchronization word,providing a second compensated DC average to the offset tracking device.11. A wireless communication device, comprising: a receiver configuredto compute a compensated DC average using a DC average and a DCcompensation factor, configured to determine whether a threshold numberof bits of a first portion of a received synchronization word asadjusted by the DC compensation factor match corresponding bits in aknown synchronization word, and configured to provide the compensated DCaverage to an offset tracker of the receiver in response to a thresholdnumber of bits of the first portion of the received synchronization wordas adjusted by the DC compensation factor matching the correspondingbits in the known synchronization word.
 12. The wireless communicationdevice according to claim 11, wherein the receiver is configured todetermine whether a threshold number of bits of a second portion of thereceived synchronization word as adjusted by the DC compensation factormatch corresponding bits in the known synchronization word, and whereinthe receiver is configured to provide a second compensated DC average tothe offset tracker in response to a threshold number of bits of thesecond portion of the received synchronization word as adjusted by theDC compensation factor matching the corresponding bits in the knownsynchronization word.
 13. The wireless communication device according toclaim 11, wherein the receiver comprises a Bluetooth-enabled receiver.14. A method for operating a wireless communication device, comprising:computing a compensated DC average using a DC average and a DCcompensation factor; determining whether a threshold number of bits of afirst portion of a received synchronization word as adjusted by the DCcompensation factor match corresponding bits in a known synchronizationword; responsive to a threshold number of bits of the first portion ofthe received synchronization word as adjusted by the DC compensationfactor matching the corresponding bits in the known synchronizationword, providing the compensated DC average to an offset tracking device;and determining whether a threshold number of bits of a second portionof the received synchronization word as adjusted by the DC compensationfactor match corresponding bits in the known synchronization word; andresponsive to a threshold number of bits of the second portion of thereceived synchronization word as adjusted by the DC compensation factormatching the corresponding bits in the known synchronization word,providing a second compensated DC average to the offset tracking device.